1. Technical Field
The present disclosure relates to a semiconductor circuit and, more particularly, to a voltage reference circuit and a current reference circuit using a vertical bipolar junction transistor (BJT) implemented by a deep N-well complementary metal-oxide semiconductor (CMOS) process.
2. Discussion of the Related Art
Generally, a bipolar junction transistor (BJT) has better junction characteristics between elements than a metal-oxide semiconductor (MOS). Meanwhile, some circuits require BJT characteristics to perform a particular function. Accordingly, it is necessary to simultaneously implement a MOS device and a BJT device in a single process. A bipolar complementary metal-oxide semiconductor (BiCMOS) process referring to the integration of a CMOS device and a BJT device into a single device, however, requires higher manufacturing costs and a longer time for development, yet provides much lower digital circuit performance than a CMOS process. In addition, when a BJT is implemented using a CMOS process, the device characteristics of the BJT also decrease.
FIGS. 1A through 2 illustrate examples of a conventional BJT device implemented by a CMOS process.
FIG. 1A is a cross-sectional view of a conventional lateral BJT implemented by a CMOS process and FIGS. 1B and 1C illustrate device symbols of a conventional lateral BJT. Referring to FIG. 1A, an N-well 11 is formed on a P substrate 10 using a CMOS process. N+ r P+ ions are implanted or diffused into each of predetermined regions in the N-well 11 and the P substrate 10 thereby forming a base region 14, a collector region 13, and an emitter region 12. An emitter terminal E and a collector terminal C are formed on the P+ regions 12 and 13, respectively, a base terminal B is formed on the N+ region 14; a substrate terminal SUB is formed on a P+ region 15; and a gate terminal G is formed at a predetermined portion on the N-well 11.
As is illustrated in FIG. 1A, a lateral PNP BJT Q1 can be obtained in a normal CMOS process. However, parasitic BJTs Q2 and Q3 are also generated during the process of obtaining the lateral PNP BJT Q1.
FIGS. 1B and 1C are symbols illustrating a lateral BJT and a parasitic BJT one with the other. Referring to FIG. 1B, a lateral BJT (Q1) is formed among an emitter E, a base B, and a collector C and also a vertical parasitic BJT (Q2 or Q3) is formed among the emitter E the base B, and a substrate SUB.
Referring to FIG. 1C, a lateral BJT (Q1) is formed among an emitter E, a base B, and a collector C and also a vertical parasitic BJT (Q2 or Q3) is formed among the emitter E, a gate G, and a substrate SUB.
As described above, due to a parasitic vertical BJT, the characteristics and particularly the current gain (β) of a lateral BJT implemented by a CMOS process decrease remarkably. In addition, the parasitic capacitance between a base that is, an N-well, and a substrate is large. In a lateral BJT implemented by a CMOS process, a base width is determined by a gate length (L) of a MOSFET. When the gate length decreases, the frequency characteristics and the current gain increase. Accordingly, the frequency characteristics and the current gain may be increased through the scale-down of the gate length. The lateral BJT, however, is degraded in reproducibility, uniformity device matching, and current drivability, whereby a circuit using this lateral BJT is eventually degraded.
FIG. 2 is a cross-sectional view of a conventional substrate BJT implemented by a CMOS process. Referring to FIG. 2, an N-well 21 is formed on a P substrate 20 formed using a CMOS process. N+ or P+ ions are implanted or diffused into each of predetermined regions in the N-well 21 and the P substrate 20, thereby forming base regions 23 and 25, collector regions 22 and 26, and an emitter region 24. As a result, the substrate BJT is obtained.
Since collectors C are stuck in the substrate 20 in the substrate BJT usually used in a bandgap circuit it is difficult to use the substrate BJT in a circuit. In addition, the N-well 21 is so thick that BJT characteristics are decreased.
As described above, a lateral BJT and a substrate BJT, which are implemented by a CMOS process, have many drawbacks. Accordingly, technology capable of replacing lateral or substrate BJTs is desired for circuits implemented by a CMOS process and needing BJT operating characteristics.